This invention relates generally to high performance integrated circuits, and more particularly, to a notched gate integrated circuit configuration to reduce gate overlap capacitance.
Integrated circuit devices used in logic products, embedded DRAM (eDRAM), and future generation commodity DRAM technologies call for a continuous improvement of both transistor and circuit performances that are affected by various analog parameters. In particular, analog parameters such as parasitic capacitances are recognized as detrimental factors to the proper functioning of integrated circuits. The switching speed of logic gates in metal oxide semiconductor (MOS) integrated circuits is limited by the time required to charge and discharge the capacitances between device electrodes and between interconnecting lines and ground.
At the circuit level, the propagation delay is normally limited by the interconnection-line capacitances. At the device level, many parasitic capacitances are normally present in conventional complimentary metal oxide semiconductor (CMOS) transistors and the load capacitance CL is generally defined by the equation:
CL=Cg+Covl+Cj+Ci,
where Cg=gate capacitance, Covl=overlap capacitance, Cj=junction capacitance, and Ci=interconnect capacitance. The load capacitance CL can dramatically affect the overall performance of the circuit by increasing the gate delay xcfx84(xcfx84=CLxc3x97Vdd/Id, where Vdd is the operating Voltage and Id is the driving current).
In previous technologies the use of relatively thick ( greater than 10 nm) gate oxides (Gox) and limited use of low dose HALO implants resulted in acceptable low values of Covl and Cj, thus the load capacitance CL was low. Gate delay improvement was mainly achieved by gate shrinking and increasing Id. Virtually no load capacitance engineering was performed other than, when possible, the use of materials with low dielectric constant ∈ for spacer fabrication (i.e. using oxide instead of nitride). ∈ is the dielectric constant of the material that is between the capacitor electrodes. As can be seen from the equation C=∈xc3x97A/t, where C=capacitance, A=area of capacitor, and t=thickness of the dielectric layer, the lower the value of ∈, the lower the capacitance C.
However, in current technologies load capacitance engineering is needed because the thickness of the Gox is decreased to increase the driving current Id and strong HALO implants are needed to decrease short channel effect (SCE) occurring at short gate lengths (generally already at gate lengths less than 0.3-0.5 um). SCE is a decreased threshold voltage Vt that is undesirable because it is desired that Vt remain constant regardless of channel length.
To compensate for SCE, strong HALO implants are utilized to push the lateral regions of the source and drain outside the gate. This effectively lengthens the channel to ensure that Vt does not decrease. It provides, secondarily, for a reduced Covl, but does so at the expense of increasing another component of the load capacitance, the junction capacitance Cj. Halo implants also introduce extra processing steps that further add to the complexity and costs of manufacturing a semiconductor device.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by the present invention that is a structure having a notched gate configuration and a method for producing the same.
In a preferred embodiment structure of the present invention, the semiconductor structure comprises a dielectric substrate, a gate electrode having indentions at each side of the gate electrode, a sidewall around a lower portion of the gate electrode, a spacer formed around the gate electrode, and a source and drain electrode.
A preferred method of forming an semiconductor device having a notched gate configuration comprises forming a dielectric substrate, depositing a gate oxide layer atop the dielectric substrate, depositing a conductive film layer atop the gate oxide and a metal silicide layer over the conductive film layer, the deposition of the metal silicide layer forming a conductive stack. The method further comprises depositing a patterned silicon nitride mask layer over the conductive stack, over-etching the patterned silicon nitride mask layer whereby a small notch is formed in the metal silicide layer at each side of the patterned silicon nitride mask layer, and etching the conductive stack down to the gate oxide layer; the small notch at each side of the patterned silicon nitride mask layer causing indentions to form in the conductive stack at the sides of the conductive film layer. The process continues with the forming of an oxide sidewall, the oxide sidewall encompassing the conductive film and gate oxide layers, the oxide sidewall conforming to the shape of the indentions, the forming a spacer around the silicon nitride mask layer and conductive stack, and forming a source and a drain in the dielectric substrate whereby the indentions in the conductive stack result in decreased gate overlap between the gate and the source and drain.
One advantage of a preferred embodiment of the present invention is that it decreases the gate overlap resulting in a smaller overall load capacitance.
Another advantage of a preferred embodiment of the present invention is that smaller gate lengths are achieved (i.e. the gate length is shorter at the bottom of the gate stack, thus a smaller device and higher performances) without extra lithography effort and cost.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.